1. Technical Field of the Invention
The present invention relates to a memory cell for a static random access memory (SRAM) device, and particularly to a circuit, layout and method of fabricating an SRAM memory cell.
2. Background of the Invention
Static random access memory (SRAM) devices have existed for a number of decades. As is well known, an SRAM memory cell includes a pair of cross-coupled logic inverters that form a latch circuit to hold data representing either a logic high level or logic low level. A pair of transmission gate transistors are connected to the cross-coupled logic inverters and provide access thereto when enabled. By connecting the control or gate terminal of the transmission gate transistors to a word line and a source/drain terminal of each transmission gate transistor to a distinct bit line of a bit line pair, data is selectively written into or read from the memory cell.
A typical implementation of the cross-coupled logic inverters is with CMOS logic inverters, each having a p-channel pull-up transistor PU and an n-channel pull-down transistor PD (FIG. 1). In addition, the transmission gate transistors TG of the SRAM memory cell traditionally have been n-channel transistors due to the carrier mobility xcexcn of n-channel transistors being approximately twice the carrier mobility xcexcp of p-channel transistors.
It is important for an SRAM memory cell to be well balanced. In other words, it is important to size the transistors of an SRAM memory cell relative to each other so as to avoid a destructive read operation in which the memory cell latch formed by the cross-coupled logic inverters flips logic states due to reading the data stored in the latch.
For example, consider the conventional SRAM memory cell shown in FIG. 1 in which the bit lines are biased at Vcc at the start of a read operation. Access to the memory cell data is provided by turning on the transmission gate transistors TG. Following activation of the transmission gate transistors TG, the low side inverter of the memory cell (the logic inverter L which outputs a logic low level) sinks the Vcc charge appearing on the corresponding bit line. Initially, the voltage appearing on the output of logic inverter L rises slightly due to demands on the pull-down transistor PD thereof. In order to avoid the output of logic inverter L from rising high enough to flip the state of the memory cell, the ratio of the transistor gain factor xcex2pd of the pull-down transistor PD to the transistor gain factor xcex2tg of the corresponding transmission gate transistor must be between approximately 2:1 and 3:1. Maintaining this ratio between the pull-down transistor PD and the corresponding transmission gate transistor TG ensures that the relative drive strength of pull-down transistors PD and transmission gate transistors TG keep the drain terminal of the pull-down transistor PD below unsafe voltage levels. With both the pull-down transistor PD and the transmission gate transistor TG being n-channel transistors and noting that the equation for the transistor gain factor xcex2 for each transistor may be represented as
xcex2=[(xcexcxcex5)/tox]*[W/L],
where xcex5 and tox respectively are the permittivity and thickness of the gate insulator and W and L respectively are the width and length of the transistor channel, this ratio requirement results in the ratio of the width-to-length ratio W/L of the pull-down transistor PD to the width-to-length ratio W/L of the transmission gate transistor TG being between 2:1 and 3:1.
As can be seen, a similar requirement exists for the transmission gate transistors TG relative to the pull-up transistors PU of the high side inverter if the bit lines are initially biased at Vss (also taking into consideration the differences in mobility between the n-channel transmission gate transistors TG and the p-channel pull-up transistors PU).
Based upon this transistor size requirement to prevent a destructive read operation from occurring, the n-channel transmission gate transistors TG in a conventional SRAM memory cell are sized differently from the n-channel pull-down transistors PD of the logic inverters in the memory cell. An existing layout of an SRAM memory cell is shown in FIG. 2, wherein the active area An in which the n-channel transistors of the memory cell are located includes a wider portion An1 over which the two pull-down transistors PD of the logic inverters are defined, and a thinner portion An2 over which the two transmission gate transistors TG of the memory cell are defined.
One problem in fabricating existing SRAM memory cells having active areas with this type of shape is a phenomenon known as round-off. Round-off may usually occur when SRAM devices are fabricated on a semiconductor wafer using photolithographic techniques to reduce or scale the size of the SRAM device to achieve smaller dimensions. Specifically, corners C1 of areas defining source/drain diffusion areas of pull-down transistors PD in the SRAM memory cell are typically rounded when defined in the semiconductor substrate relative to the substantially squared corners defined on a corresponding photolithographic mask. Such rounding of diffusion corners C1 adversely affects the performance of the corresponding transistor formed thereby.
Another problem experienced in fabricating existing SRAM devices is the potential for misalignment between layers of semiconductor material defining SRAM memory cell transistors, such as misalignment between gate polysilicon segments P and proximately located active areas An1 and/or source/drain diffusion areas. To combat misalignment, polysilicon segments P are spaced a distance D from active areas An1 and/or diffusion areas, which disadvantageously increase the size of the memory cell.
Based upon the foregoing, there is a need for an improved SRAM memory cell having a circuit and a layout that results in a more scalable memory cell without being adversely affected by phenomena such as round-off and misalignment of layers defining the memory cell transistors.
The present invention overcomes shortcomings in prior SRAM memory cells and satisfies a significant need for an SRAM memory cell having improved scalability and which is not adversely affected by round-off or misalignment phenomena. According to a preferred embodiment of the present invention, the pass gate transistors of the SRAM memory cell are p-channel transistors. Because the mobility xcexcn of n-type semiconductor material is approximately twice the mobility xcexcp of p-type semiconductor material and for a given minimum channel length L among the transistors, the width of each n-channel pull-down transistor need only be 1.0 to 1.5 times the width of the corresponding p-channel pass gate transistor in order to maintain the ratio of the transistor gain factor of the two transistors between approximately 2:1 and 3:1. Consequently, the size of the memory cell layout is reduced.
In order to improve the yield and scalability of the SRAM device, the active area for the p-channel transmission gate transistors and the p-channel pull-up transistors for each memory cell is substantially rectangular. The active area for the p-channel transistors of each memory cell abut similar active areas in adjacent memory cells in a row of memory cells, resulting in the individual active areas for the p-channel transistors forming a single rectangular active area. The active area for the n-channel transistors for each cell is also substantially rectangular. Because the active area for the p-channel transistors are substantially rectangular, round-off has less effect on memory cell performance and misalignment between the polysilicon gate segments to proximately located active areas is substantially reduced. In this way, the memory cell, according to the preferred embodiment of the present invention, is not only smaller but has improved yield.